PLL

Description

This is a wide-band Integer-N PLL incorporating optimized dynamically biased switched-capacitor (DB-SC) bank structure in the VCO for a wide tuning range.

Key Features

  • VCO Range 1.54-2.47GHz
  • Supply Voltage 1.2/2.5V
  • 35mW Power Consumption
  • Channel spacing 25MHz
  • Loop Bandwidth of 200KHz
  • PLL Phase Noise:
    -61dBc/Hz @10kHz,
    -94.53dBc/Hz @100kHz,
    -125.12dBc/Hz @1MHz,
    -136.23dBc/Hz @10MHz

  • Settling Time 25┬Ás
  • Reference spur -64.7dBm
  • Output power -2dBm
  • RMS Jitter of 5ps
  • CMOS 65nm Technology
  • KVCO of 1.3GHz/V